6553 Commits

Author	SHA1	Message	Date
Disty0	2f7aff5250	Fix TAESD previews with PixArt	2025-06-06 19:43:00 +03:00
Disty0	5624671191	Fix PixArt Sigma Small and Large	2025-06-06 19:25:26 +03:00
Disty0	089e437708	Don't set attention processors with models outside of SD 1.5 and SDXL	2025-06-06 18:53:57 +03:00
Disty0	c039ba90f6	Fix Meissonic by adding multiple generator support	2025-06-06 18:02:49 +03:00
Disty0	7679028c1a	Override CPU to use FP32 by default	2025-06-06 15:33:51 +03:00
Disty0	2ccc76ab91	Increase medvram mode to 12 GB and update wiki	2025-06-06 15:27:30 +03:00
Disty0	9a54efda9b	Cleanup	2025-06-06 01:55:35 +03:00
Disty0	06fcc3cf85	SDNQ add quantized matmul support for Conv1d and Conv3d too	2025-06-06 00:19:54 +03:00
Disty0	976f0ba61f	Cleanup	2025-06-05 20:59:58 +03:00
Disty0	413cf54cb6	Update changelog	2025-06-05 18:11:36 +03:00
Disty0	8c03f78197	Fix bias is None	2025-06-05 14:37:00 +03:00
Disty0	1a00517338	SDNQ FP8 matmul support for Conv2d	2025-06-05 14:32:26 +03:00
Disty0	9b55ffe449	SDNQ fix VAE x2	2025-06-05 14:17:59 +03:00
Disty0	ad2a4ad616	Cleanup	2025-06-05 13:38:04 +03:00
Disty0	e25890bb1d	SDNQ INT8 matmul support for Conv2d	2025-06-05 13:36:49 +03:00
Disty0	c7fb5b1690	SDNQ fix VAE quant	2025-06-05 13:24:02 +03:00
Disty0	ce3a6e27fa	SDNQ use channelwise only quant	2025-06-03 12:30:19 +03:00
Disty0	79ec23dd9d	SDNQ override conv dtype	2025-06-03 02:37:29 +03:00
Disty0	e9ff242e03	SDNQ add group size support for convs	2025-06-03 02:16:52 +03:00
Disty0	6f637f41cc	Use tensorwise fp8 matmul with torch < 2.5	2025-06-02 23:28:49 +03:00
Disty0	3f3a986c0e	SDNQ fix scale staying in fp32 with tensorwise fp8 matmul	2025-06-02 23:18:28 +03:00
Disty0	4e3795a0a5	SDNQ fix packed int8 matmul	2025-06-02 03:31:51 +03:00
Disty0	82f5634d53	SDNQ use torch.bool for uint1	2025-06-02 01:39:51 +03:00
Disty0	ea7fe3bb73	OpenVINO update dtype_mapping	2025-06-02 01:11:41 +03:00
Disty0	e8588c91ea	SDNQ enable matmul support for float8_e5m2	2025-06-02 00:53:10 +03:00
Disty0	8f1a1d7311	SDNQ expand quantized_matmul_dtypes for CPU	2025-06-02 00:28:29 +03:00
Disty0	b146025a5e	SDNQ add int2	2025-06-02 00:17:39 +03:00
Disty0	9669b36010	SDNQ fix older PyTorch with FP8 matmul	2025-06-01 23:29:16 +03:00
Disty0	acefa58834	SDNQ don't force fp32 with fp8 tensorwise matmul	2025-06-01 23:16:00 +03:00
Disty0	839295f79a	Add fp8 fnuz to sdnq options	2025-06-01 23:10:08 +03:00
Disty0	539fae3234	Update naming	2025-06-01 21:01:56 +03:00
Disty0	cefe460052	SDNQ skip FP8 matmul for input len < 32	2025-05-31 01:27:59 +03:00
Disty0	046840c8be	Fix HiDream sampling	2025-05-31 00:52:56 +03:00
Disty0	109c0d7e49	SDNQ use tensorwise FP8 matmul on CPU	2025-05-30 21:09:53 +03:00
Disty0	959b759721	Cleanup	2025-05-30 16:45:59 +03:00
Disty0	b5d588fa45	SDNQ remove unnecessary bitwise ands	2025-05-30 16:29:59 +03:00
Disty0	db816d7088	Cleanup	2025-05-30 16:02:26 +03:00
Disty0	c85cc6b397	SDNQ enable quant with GPU by default and don't do unnecessary clones	2025-05-30 15:21:29 +03:00
Disty0	4654acde3c	SDNQ re-enable memory fix for diffusers	2025-05-30 14:59:45 +03:00
Disty0	87a801e24d	SDNQ remove memory fix hijack	2025-05-30 13:54:49 +03:00
Disty0	f81cb22c00	SDNQ fix new transformers	2025-05-30 13:32:03 +03:00
Disty0	36febda6e6	SDNQ update supported dtypes	2025-05-30 13:07:23 +03:00
Disty0	29bd2af779	SDNQ add 6-bit support	2025-05-30 12:20:13 +03:00
Vladimir Mandic	98a11fc86c	fix gallery duplicate entries ... Signed-off-by: Vladimir Mandic <mandic00@live.com>	2025-05-30 11:04:56 +02:00
Disty0	d1491962d9	One bit	2025-05-30 05:41:02 +03:00
Disty0	3c8be0f55f	SDNQ add uint2	2025-05-30 04:47:29 +03:00
Disty0	599224d392	SDNQ reduce 5 reshape ops to 2 with quantized input	2025-05-30 01:31:41 +03:00
Disty0	d8dea9031f	SDNQ do FP8 matmul shape check only once	2025-05-30 01:13:37 +03:00
Disty0	b4e615e760	SDNQ add FP8 row wise scaling workaround for SM89 on Windows	2025-05-30 00:16:54 +03:00
Disty0	54154cf698	Cleanup	2025-05-29 20:22:49 +03:00