Commit Graph

10 Commits

Author SHA1 Message Date
Vladimir Mandic cb7bc0faca fix grid with lora, add dlss framgen logging, add 8bit minimax variants
Signed-off-by: Vladimir Mandic <mandic00@live.com>
2026-09-14 11:34:37 +02:00
Vladimir Mandic 14fd01f606 modular pipelines exception logging
Signed-off-by: Vladimir Mandic <mandic00@live.com>
2026-09-05 10:14:23 +02:00
Vladimir Mandic 1a47736c66 fix model-recompile keep state
Signed-off-by: Vladimir Mandic <mandic00@live.com>
2026-09-04 09:49:12 +02:00
Vladimir Mandic bed6bfc530 minimax preview
Signed-off-by: Vladimir Mandic <mandic00@live.com>
2026-08-31 17:13:11 +02:00
Vladimir Mandic b8ba831a56 minimax vae preview
Signed-off-by: Vladimir Mandic <mandic00@live.com>
2026-08-31 14:40:40 +02:00
Vladimir Mandic dbd243fe06 refactor transformers hooks
Signed-off-by: Vladimir Mandic <mandic00@live.com>
2026-08-31 13:06:02 +02:00
Vladimir Mandic a637d57ea5 modular cleanup
Signed-off-by: Vladimir Mandic <mandic00@live.com>
2026-08-29 17:40:04 +02:00
Vladimir Mandic 525e8dec9d modular set latents and steps
Signed-off-by: Vladimir Mandic <mandic00@live.com>
2026-08-29 16:20:57 +02:00
CalamitousFelicitousness d75abce642 feat(attention): sparse attention settings and router stage
Sparse attention is a stage over the chain rather than a member of it:
one switch, and the router hands the selection to whichever active
backend advertises that it consumes a block mask, currently flex. A
backend declares that through a capability set, so the quantized kernel
joins later without touching the router.

The stage gates on the component role, self attention, a minimum
sequence length defaulting to the measured 8192 token crossover, and the
absence of a token mask or causal flag, which flex cannot combine with a
block only mask. Budgets follow a precomputed per step schedule with at
most two distinct values. Enabling the feature with no capable backend
in the chain warns and leaves attention dense rather than doing nothing
quietly.

The modular pre-forward hook now receives kwargs and publishes whatever
token layout the pipeline passes by name, so a packed sequence gets its
conditioning pinned without any model specific code. Without a layout
the whole sequence is sparsified and that is logged once per length.
2026-08-28 12:40:22 +01:00
Vladimir Mandic 68d892e6b2 modular pipelines intercepts and profiling
Signed-off-by: Vladimir Mandic <mandic00@live.com>
2026-08-28 13:32:14 +02:00