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cuda : enable i16 and i32 for DUP (#28897)
* cuda : enable i16 and i32 for DUP * docs : update ops table for DUP on CUDA
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@@ -589,6 +589,14 @@ void ggml_cuda_cpy(ggml_backend_cuda_context & ctx, const ggml_tensor * src0, gg
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ggml_cpy_scalar_cuda<int32_t, int32_t>
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(src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream);
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}
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} else if (src0->type == GGML_TYPE_I16 && src1->type == GGML_TYPE_I16) {
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if (can_be_transposed) {
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ggml_cpy_scalar_cuda<int16_t, int16_t, true>
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(src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream);
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} else {
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ggml_cpy_scalar_cuda<int16_t, int16_t>
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(src0_ddc, src1_ddc, ne, ne00, ne01, ne02, nb00, nb01, nb02, nb03, ne10, ne11, ne12, nb10, nb11, nb12, nb13, main_stream);
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}
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} else if (src0->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_I32) {
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if (contiguous_srcs) {
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ggml_cpy_scalar_contiguous_cuda<float, int32_t>
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@@ -5298,10 +5298,7 @@ static bool ggml_backend_cuda_device_supports_op(ggml_backend_dev_t dev, const g
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return false;
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} break;
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case GGML_OP_DUP:
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{
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ggml_type src0_type = op->src[0]->type;
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return src0_type != GGML_TYPE_I32 && src0_type != GGML_TYPE_I16;
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} break;
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return true;
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case GGML_OP_ARGMAX:
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case GGML_OP_COUNT_EQUAL:
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{
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