diff --git a/ggml/src/ggml-cuda/allreduce.cuh b/ggml/src/ggml-cuda/allreduce.cuh
index f14ff4b617..dbeedb63c0 100644
--- a/ggml/src/ggml-cuda/allreduce.cuh
+++ b/ggml/src/ggml-cuda/allreduce.cuh
@@ -13,7 +13,7 @@ static constexpr size_t GGML_CUDA_AR_MAX_BYTES = 256 * 1024; // 256 KB
 // Opaque pipeline context — owns all pinned buffers, streams, and events.
 struct ggml_cuda_ar_pipeline;
 
-// Allocate and warm up a pipeline for n_devices GPUs.
+// Allocate a pipeline for n_devices GPUs.
 // devices[] holds the CUDA device IDs in rank order.
 // max_bytes is the staging buffer size per device; must be at least as large
 // as the largest tensor that will be reduced.
@@ -26,7 +26,7 @@ void ggml_cuda_ar_pipeline_free(ggml_cuda_ar_pipeline * pipeline);
 
 // Execute an in-place AllReduce (sum) across tensors[0..n_devices-1].
 // tensors[i] must live on the device managed by backends[i] and be
-// contiguous FP32.
+// contiguous F32, F16, or BF16.
 // Returns true on success.  Returns false when the tensor type or size is
 // outside the currently supported range; the caller should fall back to
 // another provider (NCCL or the meta-backend CPU reduce).
@@ -34,3 +34,4 @@ bool ggml_cuda_ar_allreduce(
     ggml_cuda_ar_pipeline * pipeline,
     ggml_backend_t        * backends,
     ggml_tensor           ** tensors);
+** tensors);