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mirror of https://github.com/vladmandic/automatic synced 2026-09-19 01:04:32 +02:00
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shared repos match multiple

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Signed-off-by: Vladimir Mandic <mandic00@live.com>
This commit is contained in:
Vladimir Mandic
2026-07-19 10:27:18 +02:00
parent 42cb4cf489
commit 5d989a6cc6
3 changed files with 13 additions and 29 deletions
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data/previews.json
+1
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@@ -32,6 +32,7 @@
"vladmandic--Anima-1.0-Base-sdnq-svd-dynamic-uint4": "vladmandic--Anima-1.0-Base.jpg",
"vladmandic--Anima-1.0-Turbo-sdnq-svd-dynamic-uint4": "vladmandic--Anima-1.0-Turbo.jpg",
"vladmandic--Flux.2-Klein-9B-KV-sdnq-hadamard-uint4": "black-forest-labs--FLUX.2-klein-9b-kv.jpg",
"vladmandic--Flux.2-Klein-9B-KV-Merge-sdnq-hadamard-uint4": "black-forest-labs--FLUX.2-klein-9b-kv.jpg",
"vladmandic--Krea-2-Base-sdnq-hadamard-uint4": "CalamitousFelicitousness--Krea-2-Base-Diffusers.jpg",
"vladmandic--Krea-2-Turbo-sdnq-hadamard-uint4": "CalamitousFelicitousness--Krea-2-Turbo-Diffusers.jpg",
"vladmandic--Krea-2-Turbo-Merge-sdnq-hadamard-uint4": "CalamitousFelicitousness--Krea-2-Turbo-Diffusers.jpg",
pipelines/generic_shared.py
+5 -28
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@@ -34,13 +34,7 @@ shared_te_map = {
'Qwen-2.5 SDNQ-4Bit': {
'cls': transformers.Qwen2_5_VLForConditionalGeneration,
'identifier': 'sdnq-4bit',
'target_repo': 'Disty0/Qwen-Image-2512-SDNQ-uint4-svd-r32',
'target_subfolder': 'text_encoder',
},
'Qwen-2.5 SDNQ-UInt4': {
'cls': transformers.Qwen2_5_VLForConditionalGeneration,
'identifier': 'sdnq-uint4',
'identifier': ['sdnq-4bit', 'sdnq-uint4'],
'target_repo': 'Disty0/Qwen-Image-2512-SDNQ-uint4-svd-r32',
'target_subfolder': 'text_encoder',
},
@@ -52,19 +46,7 @@ shared_te_map = {
'Qwen-3 9B SDNQ-4bit': {
'cls': transformers.Qwen3ForCausalLM,
'identifier': '9b-sdnq-4bit',
'target_repo': 'Disty0/FLUX.2-klein-9B-SDNQ-4bit-dynamic-svd-r32',
'target_subfolder': 'text_encoder',
},
'Qwen-3 9B SDNQ-UInt4': {
'cls': transformers.Qwen3ForCausalLM,
'identifier': '9b-sdnq-uint4',
'target_repo': 'Disty0/FLUX.2-klein-9B-SDNQ-4bit-dynamic-svd-r32',
'target_subfolder': 'text_encoder',
},
'Qwen-3 9B SDNQ-Hadamard-UInt4': {
'cls': transformers.Qwen3ForCausalLM,
'identifier': '9b-sdnq-hadamard-uint4',
'identifier': ['9b-sdnq-4bit', '9b-sdnq-uint4', '9b-sdnq-hadamard-uint4', '9b-kv-merge-sdnq-hadamard-uint4'],
'target_repo': 'Disty0/FLUX.2-klein-9B-SDNQ-4bit-dynamic-svd-r32',
'target_subfolder': 'text_encoder',
},
@@ -75,15 +57,9 @@ shared_te_map = {
'target_subfolder': 'text_encoder',
},
'Qwen-3 4B SDNQ-4Bit': { # match after 9b
'Qwen-3 4B SDNQ-4Bit': {
'cls': transformers.Qwen3ForCausalLM,
'identifier': 'sdnq-4bit',
'target_repo': 'Disty0/Z-Image-Turbo-SDNQ-uint4-svd-r32',
'target_subfolder': 'text_encoder',
},
'Qwen-3 4B SDNQ-UInt4': {
'cls': transformers.Qwen3ForCausalLM,
'identifier': 'sdnq-uint4',
'identifier': ['sdnq-4bit', 'sdnq-uint4'],
'target_repo': 'Disty0/Z-Image-Turbo-SDNQ-uint4-svd-r32',
'target_subfolder': 'text_encoder',
},
@@ -110,6 +86,7 @@ shared_te_map = {
'identifier': 'krea',
'target_repo': 'Qwen/Qwen3-VL-4B-Instruct',
},
'Qwen3-VL 8B SDNQ-UInt4': {
'cls': transformers.Qwen3VLModel,
'identifier': 'uint4',
pipelines/generic_text_encoder.py
+7 -1
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@@ -16,7 +16,13 @@ def get_shared(cls, repo_id, subfolder=None, variant=None):
if variant is not None:
args['variant'] = variant
for name, item in shared_te_map.items():
if item['cls'] == cls and (item.get('identifier', None) is None or item.get('identifier', None).lower() in repo_id.lower()):
identifiers = item.get('identifier', [])
if identifiers is None:
identifiers = []
if isinstance(identifiers, str):
identifiers = [identifiers]
identifiers = [identifier.lower() for identifier in identifiers if identifier is not None]
if item['cls'] == cls and (not identifiers or any(identifier in repo_id.lower() for identifier in identifiers)):
if item.get('config_class', None) is not None and item.get('config_path', None) is not None:
with open(item['config_path'], encoding='utf8') as f:
args['config'] = item['config_class'](**json.load(f))