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Author SHA1 Message Date
Disty0 64f49fb40f ROCm log HSA_OVERRIDE_GFX_VERSION skip 2025-06-11 14:58:12 +03:00
Disty0 c81b712ddb Make VAE options not require model reload 2025-06-10 15:56:19 +03:00
Disty0 78f99abec8 SDNQ use group_size / 2 for convs 2025-06-10 15:29:24 +03:00
Disty0 4436a583aa Cleanup 2025-06-10 14:12:49 +03:00
Disty0 7ccd94ed4f Force upgrade pip when installing Torch 2025-06-10 13:59:32 +03:00
Disty0 a6b58efe45 ROCm 6.4 support with --use-nightly 2025-06-10 13:42:43 +03:00
Disty0 d2ffee1b4e ROCm don't override user set HSA_OVERRIDE_GFX_VERSION 2025-06-10 13:21:37 +03:00
Disty0 f5b575db28 Update changelog and wiki 2025-06-10 12:39:34 +03:00
Disty0 33fadf946b SDNQ add 7 bit support 2025-06-10 11:33:06 +03:00
Disty0 5bd7a08877 don't use inplace ops in quant layer 2025-06-10 03:29:07 +03:00
Disty0 5eed9135e3 Split SDNQ into multiple files and linting 2025-06-10 03:18:25 +03:00
Disty0 58b646e7f2 SDNQ add 5-bit and 3-bit quantization support 2025-06-10 01:48:51 +03:00
Disty0 92dbf3941b Update changelog 2025-06-09 23:06:39 +03:00
Disty0 bd2d9d1677 Python 3.13 support 2025-06-09 22:58:08 +03:00
Disty0 92d2379626 Relax Python version check with Zluda 2025-06-09 20:18:03 +03:00
Disty0 8e08ef0edc Fix VAE Tiling with non-default tile sizes 2025-06-07 01:25:08 +03:00
Disty0 2f7aff5250 Fix TAESD previews with PixArt 2025-06-06 19:43:00 +03:00
Disty0 5624671191 Fix PixArt Sigma Small and Large 2025-06-06 19:25:26 +03:00
Disty0 089e437708 Don't set attention processors with models outside of SD 1.5 and SDXL 2025-06-06 18:53:57 +03:00
Disty0 c039ba90f6 Fix Meissonic by adding multiple generator support 2025-06-06 18:02:49 +03:00
Disty0 7679028c1a Override CPU to use FP32 by default 2025-06-06 15:33:51 +03:00
Disty0 2ccc76ab91 Increase medvram mode to 12 GB and update wiki 2025-06-06 15:27:30 +03:00
Disty0 b5d6b57500 Update PyTorch to 2.7.1 2025-06-06 11:37:10 +03:00
Disty0 9a54efda9b Cleanup 2025-06-06 01:55:35 +03:00
Disty0 06fcc3cf85 SDNQ add quantized matmul support for Conv1d and Conv3d too 2025-06-06 00:19:54 +03:00
Disty0 976f0ba61f Cleanup 2025-06-05 20:59:58 +03:00
Disty0 6bcd335f37 Update changelog and wiki 2025-06-05 20:17:46 +03:00
Disty0 778ca0436b Update wiki 2025-06-05 19:26:22 +03:00
Disty0 413cf54cb6 Update changelog 2025-06-05 18:11:36 +03:00
Disty0 8c03f78197 Fix bias is None 2025-06-05 14:37:00 +03:00
Disty0 1a00517338 SDNQ FP8 matmul support for Conv2d 2025-06-05 14:32:26 +03:00
Disty0 9b55ffe449 SDNQ fix VAE x2 2025-06-05 14:17:59 +03:00
Disty0 ad2a4ad616 Cleanup 2025-06-05 13:38:04 +03:00
Disty0 e25890bb1d SDNQ INT8 matmul support for Conv2d 2025-06-05 13:36:49 +03:00
Disty0 c7fb5b1690 SDNQ fix VAE quant 2025-06-05 13:24:02 +03:00
Disty0 1c508fbda4 Merge pull request #3960 from vladmandic/master 
Merge pull request #3957 from vladmandic/dev
 2025-06-03 18:13:47 +03:00
Disty0 0777f67573 Update changelog 2025-06-03 18:12:12 +03:00
Disty0 ce3a6e27fa SDNQ use channelwise only quant 2025-06-03 12:30:19 +03:00
Disty0 79ec23dd9d SDNQ override conv dtype 2025-06-03 02:37:29 +03:00
Disty0 e9ff242e03 SDNQ add group size support for convs 2025-06-03 02:16:52 +03:00
Disty0 6f637f41cc Use tensorwise fp8 matmul with torch < 2.5 2025-06-02 23:28:49 +03:00
Disty0 3f3a986c0e SDNQ fix scale staying in fp32 with tensorwise fp8 matmul 2025-06-02 23:18:28 +03:00
Vladimir Mandic 3ca9f29c8f Merge pull request #3957 from vladmandic/dev 
merge dev
 2025-06-02 15:52:22 +02:00
Vladimir Mandic 7d05bed459 update changelog 
Signed-off-by: Vladimir Mandic <mandic00@live.com>
 2025-06-02 15:50:42 +02:00
Vladimir Mandic f147bca20f Merge branch 'master' into dev 2025-06-02 15:45:38 +02:00
Vladimir Mandic b1d6897621 update changelog 
Signed-off-by: Vladimir Mandic <mandic00@live.com>
 2025-06-02 15:44:52 +02:00
Disty0 4e3795a0a5 SDNQ fix packed int8 matmul 2025-06-02 03:31:51 +03:00
Disty0 82f5634d53 SDNQ use torch.bool for uint1 2025-06-02 01:39:51 +03:00
Disty0 ea7fe3bb73 OpenVINO update dtype_mapping 2025-06-02 01:11:41 +03:00
Disty0 e8588c91ea SDNQ enable matmul support for float8_e5m2 2025-06-02 00:53:10 +03:00