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opencl: add bin kernel kernel_gemm_noshuffle_q4_k_f32_32b_trans_ila_a8_bin (#28677)
* opencl: add A8 Q4_K non-MoE binary kernel * opencl: fix layout compatibility * opencl: rename binary kernel selection helpers --------- Co-authored-by: Li He <lih@qti.qualcomm.com>
This commit is contained in:
shaofeiqi
GitHub
@@ -185,6 +185,7 @@ set(GGML_OPENCL_KERNELS
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gemv_noshuffle_q4_k_f32_o4
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gemv_noshuffle_q4_k_f32_tiled
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gemm_noshuffle_q4_k_f32
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gemv_noshuffle_q4_k_f32_32b_trans
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gemv_noshuffle_q6_k_f32
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gemv_noshuffle_q6_k_f32_o4
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gemv_noshuffle_q6_k_f32_tiled
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@@ -1185,6 +1185,8 @@ struct ggml_backend_opencl_context {
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cl_kernel kernel_convert_block_q4_k_tiled_ns; // tiled-wide convert (opt-in)
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cl_kernel kernel_gemv_noshuffle_q4_k_f32_mc3; // multi-column (N=3) verify GEMV
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cl_kernel kernel_gemm_noshuffle_q4_k_f32;
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cl_kernel kernel_gemm_noshuffle_q4_k_f32_32b_trans_ila_a8_bin;
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cl_kernel kernel_gemv_noshuffle_q4_k_f32_32b_trans;
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cl_kernel kernel_gemm_noshuffle_q4_k_q8_1_dp4a = nullptr; // dp4a (int8) dense prefill GEMM
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cl_kernel kernel_gemm_noshuffle_q4_k_q8_1_dp4a_wimg = nullptr; // dp4a dense prefill GEMM, weights via texture (X1 opt-in)
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cl_kernel kernel_gemm_noshuffle_q5_k_q8_1_dp4a = nullptr; // dp4a (int8) dense q5_K prefill GEMM
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@@ -4260,6 +4262,43 @@ static void load_cl_kernels(ggml_backend_opencl_context *backend_ctx) {
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GGML_LOG_CONT(".");
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}
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backend_ctx->kernel_gemv_noshuffle_q4_k_f32_32b_trans = nullptr;
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backend_ctx->kernel_gemm_noshuffle_q4_k_f32_32b_trans_ila_a8_bin = nullptr;
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if (backend_ctx->adreno_gen == ADRENO_GPU_GEN::X2E) {
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{
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std::string opts = std::string("-cl-std=") + opencl_c_std +
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" -cl-mad-enable "
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" -DSIMDGROUP_WIDTH=" +
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std::to_string(backend_ctx->adreno_wave_size);
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#ifdef GGML_OPENCL_EMBED_KERNELS
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const std::string kernel_src {
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#include "gemv_noshuffle_q4_k_f32_32b_trans.cl.h"
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};
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#else
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const std::string kernel_src = read_file("gemv_noshuffle_q4_k_f32_32b_trans.cl");
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#endif
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cl_program prog = build_program_from_source(backend_ctx, kernel_src.c_str(), opts);
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CL_CHECK((backend_ctx->kernel_gemv_noshuffle_q4_k_f32_32b_trans =
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clCreateKernel(prog, "gemv_noshuffle_q4_k_f32_32b_trans", &err), err));
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CL_CHECK(clReleaseProgram(prog));
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GGML_LOG_CONT(".");
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}
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if (use_adreno_bin_kernels(backend_ctx)) {
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size_t bin_size = 0;
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const char * kernel_bin = (const char *)backend_ctx->get_adreno_bin_kernel("gemm_noshuffle_q4_k_f32_32b_trans_ila_a8", &bin_size);
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if (kernel_bin && bin_size > 0) {
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cl_program bin_prog =
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build_program_from_binary(backend_ctx->context, backend_ctx->device, kernel_bin, "", bin_size);
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CL_CHECK((backend_ctx->kernel_gemm_noshuffle_q4_k_f32_32b_trans_ila_a8_bin =
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clCreateKernel(bin_prog, "kernel_gemm_noshuffle_q4_k_f32_32b_trans_ila_a8", &err), err));
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CL_CHECK(clReleaseProgram(bin_prog));
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GGML_LOG_CONT(".");
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}
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}
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}
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std::string CL_moe_compile_opts = std::string("-cl-std=") + opencl_c_std +
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" -cl-mad-enable "
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" -cl-fast-relaxed-math";
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@@ -7722,6 +7761,7 @@ static void ggml_cl_moe_combine_fused(ggml_backend_t backend, const ggml_tensor
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}
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inline bool use_q4k_tiled(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor); // defined below (used by the GLU-subgraph fuse check)
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inline bool use_q4_k_bin_kernels(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor);
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inline bool use_adreno_kernels(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor); // defined below
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static bool ggml_opencl_can_fuse(const ggml_backend_opencl_context * backend_ctx, const struct ggml_cgraph * cgraph, int node_idx, std::initializer_list<enum ggml_op> ops) {
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@@ -7776,6 +7816,10 @@ static bool ggml_opencl_can_fuse(const ggml_backend_opencl_context * backend_ctx
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if (use_q4k_tiled(backend_ctx, gate->src[0]) || use_q4k_tiled(backend_ctx, up->src[0])) {
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return false;
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}
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// q4_K bin kernel requires 32b transposed layout, not compatible with the fused gemv
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if (use_q4_k_bin_kernels(backend_ctx, gate->src[0]) || use_q4_k_bin_kernels(backend_ctx, up->src[0])) {
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return false;
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}
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// that noshuffle layout is only produced at set_tensor time when
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// use_adreno_kernels() accepts the weight (ne0 >= 512 && ne1 >= 512).
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// Smaller weights stay in the plain q4_K layout, which this kernel would
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@@ -8349,7 +8393,7 @@ inline bool enable_adreno_trans_weight_q5_K(const ggml_backend_opencl_context *b
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qh_img_width <= backend_ctx->image_max_buffer_size;
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}
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inline bool use_q4_0_ila_kernels(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) {
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inline bool use_q4_0_bin_kernels(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) {
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#ifdef GGML_OPENCL_USE_ADRENO_KERNELS
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if (!backend_ctx->kernel_gemv_noshuffle_q4_0_f32_32b_trans ||
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!backend_ctx->kernel_gemm_noshuffle_q4_0_f32_32b_trans_ila_a8_bin) {
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@@ -8442,6 +8486,21 @@ static inline bool use_flat_gemv_for_large_m_q6_K(const ggml_backend_opencl_cont
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&& tensor->ne[2] == 1 && tensor->ne[3] == 1;
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}
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inline bool use_q4_k_bin_kernels(const ggml_backend_opencl_context *backend_ctx, const ggml_tensor *tensor) {
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#ifdef GGML_OPENCL_USE_ADRENO_KERNELS
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if (!backend_ctx->kernel_gemv_noshuffle_q4_k_f32_32b_trans ||
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!backend_ctx->kernel_gemm_noshuffle_q4_k_f32_32b_trans_ila_a8_bin) {
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return false;
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}
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return (tensor->ne[0] % 256 == 0) && (tensor->ne[1] % 64 == 0) &&
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!use_q4k_tiled(backend_ctx, tensor) && !use_flat_gemv_for_large_m_q4_K(backend_ctx, tensor);
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#else
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GGML_UNUSED(backend_ctx);
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GGML_UNUSED(tensor);
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return false;
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#endif
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}
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static bool ggml_opencl_supports_op(ggml_backend_dev_t dev, const struct ggml_tensor * op) {
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ggml_backend_opencl_device_context * dev_ctx = (ggml_backend_opencl_device_context *)dev->context;
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ggml_backend_opencl_context * backend_ctx = dev_ctx->backend_ctx;
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@@ -9625,7 +9684,7 @@ static void ggml_backend_opencl_buffer_set_tensor(ggml_backend_buffer_t buffer,
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GGML_ASSERT(K % 32 == 0);
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if (use_q4_0_ila_kernels(backend_ctx, tensor)) {
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if (use_q4_0_bin_kernels(backend_ctx, tensor)) {
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cl_int err;
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cl_image_format wimg_fmt;
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cl_image_desc wimg_desc;
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@@ -10576,8 +10635,25 @@ static void ggml_backend_opencl_buffer_set_tensor(ggml_backend_buffer_t buffer,
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GGML_ASSERT(K % 32 == 0);
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// Transpose q, d, dm as ushort
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transpose_2d_as_16b(backend_ctx, extra->q, extra->q, size_q, K/4, M);
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if (use_q4_k_bin_kernels(backend_ctx, tensor)) {
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cl_int err;
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cl_image_format wimg_fmt;
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cl_image_desc wimg_desc;
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// transpose quants as 32-bit words (M-first)
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GGML_ASSERT(M % 64 == 0);
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transpose_2d_as_32b(backend_ctx, extra->q, extra->q, size_q, K/8, M);
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wimg_fmt = { CL_R, CL_UNSIGNED_INT32 };
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memset(&wimg_desc, 0, sizeof(wimg_desc));
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wimg_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER;
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wimg_desc.image_width = (size_t)M * K / 8;
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wimg_desc.buffer = extra->q;
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CL_CHECK((extra->q_img = clCreateImage(context, CL_MEM_READ_ONLY, &wimg_fmt, &wimg_desc, NULL, &err), err));
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} else {
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// Transpose q as ushort
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transpose_2d_as_16b(backend_ctx, extra->q, extra->q, size_q, K/4, M);
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}
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transpose_2d_as_16b(backend_ctx, extra->d, extra->d, size_d, K/256, M);
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transpose_2d_as_16b(backend_ctx, extra->dm, extra->dm, size_dm, K/256, M);
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@@ -11180,7 +11256,7 @@ static void ggml_backend_opencl_buffer_get_tensor(ggml_backend_buffer_t buffer,
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buf_trans_d.allocate(backend_ctx->context, size_d);
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buf_unpacked.allocate(backend_ctx->context, ggml_nbytes(tensor));
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if (use_q4_0_ila_kernels(backend_ctx, tensor)) {
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if (use_q4_0_bin_kernels(backend_ctx, tensor)) {
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transpose_2d_as_32b(backend_ctx, extra->q, buf_trans_q.buffer, size_q, M, K / 8);
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} else {
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transpose_2d_as_16b(backend_ctx, extra->q, buf_trans_q.buffer, size_q, M, K / 4);
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@@ -11855,7 +11931,11 @@ static void ggml_backend_opencl_buffer_get_tensor(ggml_backend_buffer_t buffer,
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buf_trans_s.allocate(backend_ctx->context, size_s);
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// Transpose q, d, dm, s back
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transpose_2d_as_16b(backend_ctx, extra->q, buf_trans_q.buffer, size_q, M, K/4);
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if (use_q4_k_bin_kernels(backend_ctx, tensor)) {
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transpose_2d_as_32b(backend_ctx, extra->q, buf_trans_q.buffer, size_q, M, K/8);
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} else {
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transpose_2d_as_16b(backend_ctx, extra->q, buf_trans_q.buffer, size_q, M, K/4);
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}
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transpose_2d_as_16b(backend_ctx, extra->d, buf_trans_d.buffer, size_d, M, K/256);
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transpose_2d_as_16b(backend_ctx, extra->dm, buf_trans_dm.buffer, size_dm, M, K/256);
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transpose_2d_as_8b (backend_ctx, extra->s, buf_trans_s.buffer, size_s, M, K/256*12, true, true);
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@@ -18639,9 +18719,9 @@ static void ggml_cl_mul_mat_q4_0_f32_adreno(ggml_backend_t backend, const ggml_t
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static const bool q40_mc3 = (getenv("GGML_OPENCL_Q40_MC3") != nullptr);
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const bool use_q40_mc3 = q40_mc3 && (ne1 >= 2 && ne1 <= 4) && (ne01 < 32768);
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const bool use_ila = use_q4_0_ila_kernels(backend_ctx, src0);
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const bool use_bin = use_q4_0_bin_kernels(backend_ctx, src0);
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if (use_ila) {
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if (use_bin) {
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if (use_q40_mc3) {
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static bool warned = false;
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if (!warned) {
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@@ -20196,6 +20276,145 @@ static void ggml_cl_mul_mat_q8_0_f32_adreno(ggml_backend_t backend, const ggml_t
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#endif
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}
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#ifdef GGML_OPENCL_USE_ADRENO_KERNELS
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static void ggml_cl_mul_mat_q4_k_f32_adreno_ila(ggml_backend_t backend, const ggml_tensor * src0,
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const ggml_tensor * src1, ggml_tensor * dst) {
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GGML_ASSERT(src0);
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GGML_ASSERT(src0->extra);
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GGML_ASSERT(src1);
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GGML_ASSERT(src1->extra);
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GGML_ASSERT(dst);
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GGML_ASSERT(dst->extra);
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ggml_backend_opencl_context *backend_ctx = (ggml_backend_opencl_context *)backend->context;
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ggml_tensor_extra_cl * extra1 = (ggml_tensor_extra_cl *)src1->extra;
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ggml_tensor_extra_cl * extrad = (ggml_tensor_extra_cl *)dst->extra;
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ggml_tensor_extra_cl_q4_K * extra0_q4_k = (ggml_tensor_extra_cl_q4_K *)src0->extra;
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cl_ulong offset1 = extra1->offset + src1->view_offs;
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cl_ulong offsetd = extrad->offset + dst->view_offs;
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const int ne00 = src0->ne[0];
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const int ne01 = src0->ne[1];
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const int ne1 = dst->ne[1];
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GGML_ASSERT(ne00 % ggml_blck_size(src0->type) == 0);
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cl_context context = backend_ctx->context;
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cl_kernel kernel;
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cl_int err;
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cl_image_format img_fmt;
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cl_image_desc img_desc;
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cl_buffer_region region;
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int M = ne01;
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int N = ne1;
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int K = ne00;
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if (ne1 == 1) {
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cl_mem b_sub_buf = nullptr;
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cl_mem b_img = nullptr;
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region.origin = offset1;
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region.size = (size_t)K * N * sizeof(float);
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CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err));
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img_fmt = { CL_RGBA, CL_FLOAT };
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memset(&img_desc, 0, sizeof(img_desc));
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img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER;
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img_desc.image_width = (size_t)K * N / 4;
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img_desc.buffer = b_sub_buf;
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CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err));
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kernel = backend_ctx->kernel_gemv_noshuffle_q4_k_f32_32b_trans;
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CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q4_k->q_img));
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CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_k->d));
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CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q4_k->dm));
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CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q4_k->s));
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CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &b_img));
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CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &extrad->data_device));
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CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_ulong), &offsetd));
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CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_int), &ne00));
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CL_CHECK(clSetKernelArg(kernel, 8, sizeof(cl_int), &ne01));
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size_t local_work_size[3] = { 64, 8, 1 };
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size_t global_work_size[3] = { (size_t)ne01, 8, 1 };
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backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst);
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CL_CHECK(clReleaseMemObject(b_sub_buf));
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CL_CHECK(clReleaseMemObject(b_img));
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} else {
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const int gemm_tile_n = 64;
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int N_pad = CEIL_DIV(N, gemm_tile_n) * gemm_tile_n;
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cl_mem b_sub_buf = nullptr;
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cl_mem b_padded = nullptr;
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cl_mem b_buf = nullptr;
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if (N_pad == N) {
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region.origin = offset1;
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region.size = (size_t)K * N * sizeof(float);
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CL_CHECK((b_sub_buf = clCreateSubBuffer(extra1->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err));
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b_buf = b_sub_buf;
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} else {
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CL_CHECK((b_padded = clCreateBuffer(context, CL_MEM_READ_WRITE, (size_t)K * N_pad * sizeof(float), NULL, &err), err));
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const float zero = 0.0f;
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CL_CHECK(clEnqueueFillBuffer(backend_ctx->queue, b_padded, &zero, sizeof(zero), 0, (size_t)K * N_pad * sizeof(float), 0, NULL, NULL));
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CL_CHECK(clEnqueueCopyBuffer(backend_ctx->queue, extra1->data_device, b_padded, offset1, 0, (size_t)K * N * sizeof(float), 0, NULL, NULL));
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b_buf = b_padded;
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}
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img_fmt = { CL_R, CL_FLOAT };
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memset(&img_desc, 0, sizeof(img_desc));
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img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER;
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img_desc.image_width = (size_t)K * N_pad;
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img_desc.buffer = b_buf;
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cl_mem b_img;
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CL_CHECK((b_img = clCreateImage(context, CL_MEM_READ_ONLY, &img_fmt, &img_desc, NULL, &err), err));
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region.origin = offsetd;
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region.size = (size_t)M * N * sizeof(float);
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cl_mem d_sub_buf;
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CL_CHECK((d_sub_buf = clCreateSubBuffer(extrad->data_device, 0, CL_BUFFER_CREATE_TYPE_REGION, ®ion, &err), err));
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img_fmt = { CL_R, CL_FLOAT };
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memset(&img_desc, 0, sizeof(img_desc));
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img_desc.image_type = CL_MEM_OBJECT_IMAGE1D_BUFFER;
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img_desc.image_width = (size_t)M * N;
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img_desc.buffer = d_sub_buf;
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cl_mem d_img;
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CL_CHECK((d_img = clCreateImage(context, CL_MEM_WRITE_ONLY, &img_fmt, &img_desc, NULL, &err), err));
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kernel = backend_ctx->kernel_gemm_noshuffle_q4_k_f32_32b_trans_ila_a8_bin;
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CL_CHECK(clSetKernelArg(kernel, 0, sizeof(cl_mem), &extra0_q4_k->q_img));
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CL_CHECK(clSetKernelArg(kernel, 1, sizeof(cl_mem), &extra0_q4_k->d));
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CL_CHECK(clSetKernelArg(kernel, 2, sizeof(cl_mem), &extra0_q4_k->dm));
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CL_CHECK(clSetKernelArg(kernel, 3, sizeof(cl_mem), &extra0_q4_k->s));
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CL_CHECK(clSetKernelArg(kernel, 4, sizeof(cl_mem), &b_img));
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CL_CHECK(clSetKernelArg(kernel, 5, sizeof(cl_mem), &d_img));
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CL_CHECK(clSetKernelArg(kernel, 6, sizeof(cl_uint), &ne00));
|
||||
CL_CHECK(clSetKernelArg(kernel, 7, sizeof(cl_uint), &ne01));
|
||||
CL_CHECK(clSetKernelArg(kernel, 8, sizeof(int), &N));
|
||||
|
||||
size_t local_work_size[3] = { 64, 2, 2 };
|
||||
size_t m_tiles = (size_t)CEIL_DIV(M, 64);
|
||||
size_t global_work_size[3] = { 64, m_tiles, (size_t)CEIL_DIV(N_pad, gemm_tile_n) };
|
||||
backend_ctx->enqueue_ndrange_kernel(kernel, 3, global_work_size, local_work_size, dst);
|
||||
|
||||
CL_CHECK(clReleaseMemObject(b_img));
|
||||
if (b_sub_buf) {
|
||||
CL_CHECK(clReleaseMemObject(b_sub_buf));
|
||||
}
|
||||
if (b_padded) {
|
||||
CL_CHECK(clReleaseMemObject(b_padded));
|
||||
}
|
||||
CL_CHECK(clReleaseMemObject(d_img));
|
||||
CL_CHECK(clReleaseMemObject(d_sub_buf));
|
||||
}
|
||||
}
|
||||
#endif // GGML_OPENCL_USE_ADRENO_KERNELS
|
||||
|
||||
static void ggml_cl_mul_mat_q4_k_f32_adreno(ggml_backend_t backend, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) {
|
||||
#ifdef GGML_OPENCL_USE_ADRENO_KERNELS
|
||||
GGML_ASSERT(src0);
|
||||
@@ -20248,6 +20467,20 @@ static void ggml_cl_mul_mat_q4_k_f32_adreno(ggml_backend_t backend, const ggml_t
|
||||
// unified routes batched Q6_K lm_head to CPU). Per-layer mc3 is byte-identical.
|
||||
const bool use_mc3 = q4k_mc3 && (ne1 == 3) && (ne01 < 32768);
|
||||
|
||||
const bool use_bin = use_q4_k_bin_kernels(backend_ctx, src0);
|
||||
|
||||
if (use_bin) {
|
||||
if (use_mc3) {
|
||||
static bool warned = false;
|
||||
if (!warned) {
|
||||
GGML_LOG_WARN("ggml_opencl: GGML_OPENCL_Q4K_MC3 is bypassed by Q4_K binary kernels\n");
|
||||
warned = true;
|
||||
}
|
||||
}
|
||||
ggml_cl_mul_mat_q4_k_f32_adreno_ila(backend, src0, src1, dst);
|
||||
return;
|
||||
}
|
||||
|
||||
if (ne1 == 1 || use_mc3) {
|
||||
cl_mem q_img = nullptr;
|
||||
cl_mem b_sub_buf = nullptr;
|
||||
|
||||
@@ -0,0 +1,134 @@
|
||||
#pragma OPENCL EXTENSION cl_khr_fp16 : enable
|
||||
#pragma OPENCL EXTENSION cl_khr_subgroups : enable
|
||||
#pragma OPENCL EXTENSION cl_qcom_reqd_sub_group_size : enable
|
||||
|
||||
#define QK_K 256
|
||||
#define K_SCALE_SIZE 12
|
||||
#define N_SIMDGROUP 8
|
||||
#define SIMDGROUP_WIDTH 64
|
||||
|
||||
inline void get_scale_min_k4(
|
||||
int j,
|
||||
global const uchar * q,
|
||||
uint stride,
|
||||
uchar * d,
|
||||
uchar * m
|
||||
) {
|
||||
if (j < 4) {
|
||||
*d = q[j*stride] & 63;
|
||||
*m = q[(j+4)*stride] & 63;
|
||||
} else {
|
||||
*d = (q[(j+4)*stride] & 0x0F) | ((q[(j-4)*stride] & 0xC0) >> 2);
|
||||
*m = ((q[(j+4)*stride] >> 4) & 0x0F) | ((q[j*stride] & 0xC0) >> 2);
|
||||
}
|
||||
}
|
||||
|
||||
static inline float8 q4_k_to_fp32_packed8(ushort2 q4x8, float scale, float minv) {
|
||||
float8 fp32x8;
|
||||
fp32x8.s0 = (q4x8.s0 & 0x000F) * scale - minv;
|
||||
fp32x8.s1 = ((q4x8.s0 & 0x00F0) >> 4) * scale - minv;
|
||||
fp32x8.s2 = ((q4x8.s0 & 0x0F00) >> 8) * scale - minv;
|
||||
fp32x8.s3 = ((q4x8.s0 & 0xF000) >> 12) * scale - minv;
|
||||
fp32x8.s4 = (q4x8.s1 & 0x000F) * scale - minv;
|
||||
fp32x8.s5 = ((q4x8.s1 & 0x00F0) >> 4) * scale - minv;
|
||||
fp32x8.s6 = ((q4x8.s1 & 0x0F00) >> 8) * scale - minv;
|
||||
fp32x8.s7 = ((q4x8.s1 & 0xF000) >> 12) * scale - minv;
|
||||
return fp32x8;
|
||||
}
|
||||
|
||||
__attribute__((qcom_reqd_sub_group_size("half")))
|
||||
__kernel void gemv_noshuffle_q4_k_f32_32b_trans(
|
||||
read_only image1d_buffer_t src0_q,
|
||||
__global half * src0_d,
|
||||
__global half * src0_dm,
|
||||
__global uchar * src0_s,
|
||||
__read_only image1d_buffer_t src1,
|
||||
__global float * dst,
|
||||
ulong offsetd,
|
||||
int ne00,
|
||||
int ne01
|
||||
) {
|
||||
uint i01 = get_global_id(0);
|
||||
uint sgid = get_local_id(1);
|
||||
uint slid = get_sub_group_local_id();
|
||||
|
||||
int num_subblocks = ne00 / 32;
|
||||
|
||||
__private float sum = 0.0f;
|
||||
|
||||
// Loop over sub-blocks of 32 elements, N_SIMDGROUP sub-blocks per iter
|
||||
for (uint ib = sgid; ib < num_subblocks; ib += N_SIMDGROUP) {
|
||||
uint sb = ib / 8;
|
||||
uint j = ib % 8;
|
||||
|
||||
// Load d and dmin for this super-block
|
||||
half d_val = src0_d[sb * ne01 + i01];
|
||||
half dm_val = src0_dm[sb * ne01 + i01];
|
||||
|
||||
// Load sub-block scale and min. s is transposed [nb][12][M]; stride ne01 per code.
|
||||
global const uchar * sc = src0_s + sb * K_SCALE_SIZE * ne01 + i01;
|
||||
uchar sv, mn;
|
||||
get_scale_min_k4(j, sc, ne01, &sv, &mn);
|
||||
|
||||
float scale = (float)d_val * (float)sv;
|
||||
float minv = (float)dm_val * (float)mn;
|
||||
|
||||
// Load 4 uints of quants (32 nibbles = 32 elements), column-major stride ne01
|
||||
uint q_base = ib * ne01 * 4 + i01;
|
||||
|
||||
uint4 regQ;
|
||||
regQ.s0 = read_imageui(src0_q, q_base).x;
|
||||
regQ.s1 = read_imageui(src0_q, q_base + ne01).x;
|
||||
regQ.s2 = read_imageui(src0_q, q_base + ne01 * 2).x;
|
||||
regQ.s3 = read_imageui(src0_q, q_base + ne01 * 3).x;
|
||||
|
||||
// Load activations: 32 floats = 8 float4s
|
||||
uint y_offset = ib * 8;
|
||||
|
||||
float4 y_local = (slid < 8) ? read_imagef(src1, (y_offset + slid)) : (float4)0.0f;
|
||||
float4 y0 = sub_group_broadcast(y_local, 0);
|
||||
float4 y1 = sub_group_broadcast(y_local, 1);
|
||||
float4 y2 = sub_group_broadcast(y_local, 2);
|
||||
float4 y3 = sub_group_broadcast(y_local, 3);
|
||||
float4 y4 = sub_group_broadcast(y_local, 4);
|
||||
float4 y5 = sub_group_broadcast(y_local, 5);
|
||||
float4 y6 = sub_group_broadcast(y_local, 6);
|
||||
float4 y7 = sub_group_broadcast(y_local, 7);
|
||||
|
||||
float8 fp32x8 = q4_k_to_fp32_packed8(as_ushort2(regQ.s0), scale, minv);
|
||||
float4 acc = y0 * fp32x8.lo;
|
||||
acc += y1 * fp32x8.hi;
|
||||
|
||||
fp32x8 = q4_k_to_fp32_packed8(as_ushort2(regQ.s1), scale, minv);
|
||||
acc += y2 * fp32x8.lo;
|
||||
acc += y3 * fp32x8.hi;
|
||||
|
||||
fp32x8 = q4_k_to_fp32_packed8(as_ushort2(regQ.s2), scale, minv);
|
||||
acc += y4 * fp32x8.lo;
|
||||
acc += y5 * fp32x8.hi;
|
||||
|
||||
fp32x8 = q4_k_to_fp32_packed8(as_ushort2(regQ.s3), scale, minv);
|
||||
acc += y6 * fp32x8.lo;
|
||||
acc += y7 * fp32x8.hi;
|
||||
|
||||
sum += ((acc.s0 + acc.s1) + (acc.s2 + acc.s3));
|
||||
}
|
||||
|
||||
// reduction in local memory over N_SIMDGROUP subgroups
|
||||
__local float reduceLM[SIMDGROUP_WIDTH * (N_SIMDGROUP - 1)];
|
||||
if (sgid > 0) {
|
||||
reduceLM[SIMDGROUP_WIDTH * (sgid - 1) + slid] = sum;
|
||||
}
|
||||
barrier(CLK_LOCAL_MEM_FENCE);
|
||||
if (sgid == 0) {
|
||||
for (uint i = 0; i < N_SIMDGROUP - 1; ++i) {
|
||||
sum += reduceLM[SIMDGROUP_WIDTH * i + slid];
|
||||
}
|
||||
}
|
||||
|
||||
// 1 output per thread in subgroup 0
|
||||
if (sgid == 0) {
|
||||
dst = dst + (offsetd >> 2);
|
||||
dst[i01] = sum;
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user