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fix comments
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@@ -13,7 +13,7 @@ static constexpr size_t GGML_CUDA_AR_MAX_BYTES = 256 * 1024; // 256 KB
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// Opaque pipeline context — owns all pinned buffers, streams, and events.
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struct ggml_cuda_ar_pipeline;
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// Allocate and warm up a pipeline for n_devices GPUs.
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// Allocate a pipeline for n_devices GPUs.
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// devices[] holds the CUDA device IDs in rank order.
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// max_bytes is the staging buffer size per device; must be at least as large
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// as the largest tensor that will be reduced.
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@@ -26,7 +26,7 @@ void ggml_cuda_ar_pipeline_free(ggml_cuda_ar_pipeline * pipeline);
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// Execute an in-place AllReduce (sum) across tensors[0..n_devices-1].
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// tensors[i] must live on the device managed by backends[i] and be
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// contiguous FP32.
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// contiguous F32, F16, or BF16.
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// Returns true on success. Returns false when the tensor type or size is
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// outside the currently supported range; the caller should fall back to
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// another provider (NCCL or the meta-backend CPU reduce).
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@@ -34,3 +34,4 @@ bool ggml_cuda_ar_allreduce(
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ggml_cuda_ar_pipeline * pipeline,
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ggml_backend_t * backends,
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ggml_tensor ** tensors);
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** tensors);
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